1. Field of the Invention
This invention relates generally to a data processing system with memory, and more particularly to a data processing system having a chipset with phase lock loop circuitry for synchronizing clock signal distribution for memory read/write operations.
2. Background of the Invention
With the rapid development of data processing technology, high speed devices such as the Intel Pentium II CPU chip, operating at frequencies up to 266 MHz, and SDRAMs, operating at frequencies of 100 MHz, are widely used. Though the core frequencies of CPUs and memories have risen above 100 MHz, the data buses transmitting data between the CPU and the memory chips have been limited to operating frequencies of approximately 66 MHz. The main reason for the speed discrepancy between chips and buses is that as the data bus operating frequency increases, a phase difference (clock skew) between different components located at different distances from the system clock generator becomes more serious; even to the extent of making the setup time insufficient for data strobe.
Conventional methods eliminate clock skew by designing the circuit board to have the same trace length from the different components to the system clock generator. Another approach is to employ delay elements on the shorter signal lines to produce phase delays to match the longer lines. Sometimes the phase delays need to be matched where signals run throughout various components. These phase delays then are the sum of the delay due to the circuit board signal lines plus the delay due to the components.
FIG. 1 illustrates a simplified block diagram of a conventional data processing system 190. A clock generator with a driver 101 provides skewless clock signals for a memory controller chip 102 and SDRAM 103 via signal lines 104 and 105 respectively. Memory controller 102 includes a write data buffer 106 for data write and a read data buffer 107 for data read. The clock signal is transmitted to memory controller 102 via a signal line 104 and an input pad 108 to a clock trunk 114 inside memory controller 102, and distributed to all components inside memory controller 102, including write data buffer 106 and read data buffer 107. Data is transmitted from an output pad 110 to an input port 112, and from an output port 113 to an input pad 109 via a data bus 111. Input pad 109 and output pad 110 are pads connected to the I/O pins of memory controller 102. Input port 112 and output port 113 are data ports of SDRAM 103. The data is transmitted between memory controller 102 and SDRAM 103 in accordance with a command signal for data read/write operation (the command signal is not shown in the figure).
For a read cycle, the clock signal triggers read data buffer 107 so that upon the arrival of data from SDRAM 103, there will be sufficient setup time for correct data strobe. Similarly, for a write cycle, the clock signal triggers SDRAM 103 so that upon arrival of data from write data buffer 106, there will be sufficient setup time for correct data strobe. Accordingly, for clock consistency, it is necessary to maintain the equivalent trace length from clock generator 101 to different components through signal lines such as 104 and 105.
However, as operating frequencies increase, e.g., above 100 MHz, such conventional methods may not be appropriate. This is because as the clock cycle becomes shorter, the tolerance to the deviation of trace length between signal lines is reduced. This sets an extremely stringent precision requirement which may be difficult to meet with present layout technology.
For example, under operating frequencies of 66 MHz, 100 MHz, and 133 MHz, the clock period is 15 ns, 10 ns, and 7.5 ns respectively. That means the clock period is reduced from 15 to 7.5 ns due to the increase in the operation frequency. However, with present layout technology, trace length deviations are about one inch or more between different signal lines. This will result in a phase delay of 0.25 ns between the signal lines. This will be exacerbated if the clock signal passes through various components on the circuit board. This reduced tolerance becomes critical to avoid incorrect data strobe operation resulting from insufficient setup time. In theory, the circuit board layout can be designed to achieve the required tolerances, but this will result in higher design, testing, and manufacturing costs.